Size reduction of complementary metal-oxide-semiconductor (CMOS) devices, such as transistors, has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. As sizes are reduced, there has been a trend to integrate more functions on a single chip, some of which require higher voltage levels.
Low-voltage devices are typically formed using self-aligning doping techniques in which the polysilicon gate electrode acts as a mask during implanting processes to form the source and drain regions. High-voltage devices, however, require the implanting processes to be performed at a higher energy level and a higher doping concentration to form the source/drain regions. Because of these higher energy levels and doping concentrations, the polysilicon gate electrode is not typically thick enough to prevent dopants to be improperly implanted in the channel region.
In an attempt to solve this problem, attempts have been made to place a hard mask with an overlying photoresist layer on top of the polysilicon gate electrode of the high-voltage devices. In these attempts, however, the hard mask layer on top of the polysilicon gate electrode is etched multiple times, including a wet etch followed by a dry etch using a photoresist mask. This process flow typically created a hard mask profile that created a non-uniform dopant concentration in the p-base implant region. As a result, the threshold voltage Vt is inconsistent and frequently leads to inconsistent and faulty devices.
Accordingly, there is a need for high-voltage devices that may be fabricated consistently and uniformly, particularly in conjunction with low-voltage devices.